VSCode怎么配置verilog環(huán)境？下面本篇文章給大家推薦三個(gè)插件，讓VSCode流暢編寫(xiě)verilog，三個(gè)插件可實(shí)現(xiàn)代碼提示+自動(dòng)例化+格式化。

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Verilog-HDL/SystemVerilog/Bluespec SystemVerilog

可實(shí)現(xiàn)功能：

• 語(yǔ)法高亮
• 自動(dòng)例化
• 代碼提示和跳轉(zhuǎn)
• 自動(dòng)補(bǔ)全

插件配置

如Verilog HDL/SystemVerilog插件歡迎頁(yè)的說(shuō)明，支持Ctags功能：

配置步驟：

• 下載最新版ctags，舊版的有些功能不夠齊全；windows可選x64版本；

• 將ctags.exe的路徑設(shè)置到系統(tǒng)環(huán)境變量中；

• 插件設(shè)置中配置ctags路徑；

• 重啟VSCode即可；

可以選擇不同的編譯器

包括：

• iverilog
• xvlog(vivado)
• modelsim

功能展示

支持verilog、SV等語(yǔ)法高亮。

shift+ctrl+p輸入verilog，可以直接自動(dòng)例化模塊。

鼠標(biāo)放在信號(hào)上，就會(huì)有聲明顯示在懸浮框中。Ctrl+左鍵，點(diǎn)擊信號(hào)名，自動(dòng)跳轉(zhuǎn)到聲明處。光標(biāo)放在信號(hào)處，右鍵選擇查看定義（快捷鍵可自行綁定），可以在此處展開(kāi)聲明處的代碼，用于修改聲明十分方便，就不用再來(lái)回跳轉(zhuǎn)了。

Verilog_Testbench

可實(shí)現(xiàn)功能：

• 自動(dòng)生成testbench

shift+ctrl+p輸入testbench，可以直接生成tb。然后在終端復(fù)制即可。

SystemVerilog and Verilog Formatter

這款工具由谷歌推出，同時(shí)支持Verilog和System Verilog，效果非常好，支持自定義的格式化參數(shù)也很豐富。個(gè)人認(rèn)為比verilog format好用。

可實(shí)現(xiàn)功能

• 自動(dòng)格式化文件
• 自動(dòng)格式化選定內(nèi)容
• 自定義格式

自定義參數(shù)設(shè)置表

verible-verilog-format: usage: bazel-bin/verilog/tools/formatter/verible-verilog-format [options] <file> [<file…>]
To pipe from stdin, use '-' as <file>.

Flags from common/formatting/basic_format_style_init.cc:
–column_limit (Target line length limit to stay under when formatting.);
default: 100;
–indentation_spaces (Each indentation level adds this many spaces.);
default: 2;
–line_break_penalty (Penalty added to solution for each introduced line
break.); default: 2;
–over_column_limit_penalty (For penalty minimization, this represents the
baseline penalty value of exceeding the column limit. Additional penalty
of 1 is incurred for each character over this limit); default: 100;
–wrap_spaces (Each wrap level adds this many spaces. This applies when the
first element after an open-group section is wrapped. Otherwise, the
indentation level is set to the column position of the open-group
operator.); default: 4;

Flags from external/com_google_absl/absl/flags/parse.cc:
–flagfile (comma-separated list of files to load flags from); default: ;
–fromenv (comma-separated list of flags to set from the environment [use
'export FLAGS_flag1=value']); default: ;
–tryfromenv (comma-separated list of flags to try to set from the
environment if present); default: ;
–undefok (comma-separated list of flag names that it is okay to specify on
the command line even if the program does not define a flag with that
name); default: ;

Flags from verilog/formatting/format_style_init.cc:
–assignment_statement_alignment (Format various assignments:
{align,flush-left,preserve,infer}); default: infer;
–case_items_alignment (Format case items:
{align,flush-left,preserve,infer}); default: infer;
–class_member_variable_alignment (Format class member variables:
{align,flush-left,preserve,infer}); default: infer;
–compact_indexing_and_selections (Use compact binary expressions inside
indexing / bit selection operators); default: true;
–distribution_items_alignment (Aligh distribution items:
{align,flush-left,preserve,infer}); default: infer;
–enum_assignment_statement_alignment (Format assignments with enums:
{align,flush-left,preserve,infer}); default: infer;
–expand_coverpoints (If true, always expand coverpoints.); default: false;
–formal_parameters_alignment (Format formal parameters:
{align,flush-left,preserve,infer}); default: infer;
–formal_parameters_indentation (Indent formal parameters: {indent,wrap});
default: wrap;
–module_net_variable_alignment (Format net/variable declarations:
{align,flush-left,preserve,infer}); default: infer;
–named_parameter_alignment (Format named actual parameters:
{align,flush-left,preserve,infer}); default: infer;
–named_parameter_indentation (Indent named parameter assignments:
{indent,wrap}); default: wrap;
–named_port_alignment (Format named port connections:
{align,flush-left,preserve,infer}); default: infer;
–named_port_indentation (Indent named port connections: {indent,wrap});
default: wrap;
–port_declarations_alignment (Format port declarations:
{align,flush-left,preserve,infer}); default: infer;
–port_declarations_indentation (Indent port declarations: {indent,wrap});
default: wrap;
–port_declarations_right_align_packed_dimensions (If true, packed
dimensions in contexts with enabled alignment are aligned to the right.);
default: false;
–port_declarations_right_align_unpacked_dimensions (If true, unpacked
dimensions in contexts with enabled alignment are aligned to the right.);
default: false;
–struct_union_members_alignment (Format struct/union members:
{align,flush-left,preserve,infer}); default: infer;
–try_wrap_long_lines (If true, let the formatter attempt to optimize line
wrapping decisions where wrapping is needed, else leave them unformatted.
This is a short-term measure to reduce risk-of-harm.); default: false;

Flags from verilog/parser/verilog_parser.cc:
–verilog_trace_parser (Trace verilog parser); default: false;

Flags from verilog/tools/formatter/verilog_format.cc:
–failsafe_success (If true, always exit with 0 status, even if there were
input errors or internal errors. In all error conditions, the original
text is always preserved. This is useful in deploying services where
fail-safe behaviors should be considered a success.); default: true;
–inplace (If true, overwrite the input file on successful conditions.);
default: false;
–lines (Specific lines to format, 1-based, comma-separated, inclusive N-M
ranges, N is short for N-N. By default, left unspecified, all lines are
enabled for formatting. (repeatable, cumulative)); default: ;
–max_search_states (Limits the number of search states explored during line
wrap optimization.); default: 100000;
–show_equally_optimal_wrappings (If true, print when multiple optimal
solutions are found (stderr), but continue to operate normally.);
default: false;
–show_inter_token_info (If true, along with show_token_partition_tree,
include inter-token information such as spacing and break penalties.);
default: false;
–show_largest_token_partitions (If > 0, print token partitioning and then
exit without formatting output.); default: 0;
–show_token_partition_tree (If true, print diagnostics after token
partitioning and then exit without formatting output.); default: false;
–stdin_name (When using '-' to read from stdin, this gives an alternate
name for diagnostic purposes. Otherwise this is ignored.);
default: "<stdin>";
–verbose (Be more verbose.); default: false;
–verify_convergence (If true, and not incrementally formatting with
–lines, verify that re-formatting the formatted output yields no further
changes, i.e. formatting is convergent.); default: true;

Try –helpfull to get a list of all flags or –help=substring shows help for
flags which include specified substring in either in the name, or description or
path.

插件配置

如果是windows，systemverilogFormatter.veribleBuild設(shè)置為win64

systemverilogFormatter.commandLineArguments可以自定義格式化參數(shù)，下面放上我自己用的參數(shù)，可以實(shí)現(xiàn)大部分常用代碼段實(shí)現(xiàn)對(duì)齊。

--indentation_spaces=4 --named_port_alignment=align  --ort_declarations_alignment=align --module_net_variable_alignment=align

如何使用？如何格式化？

和vscode內(nèi)置格式化一樣，直接shift+ctrl+f就可以格式化文件，ctrl+k可以格式化選定內(nèi)容。

值得注意的是，由于這個(gè)插件也是在完善中，還是存在部分問(wèn)題的。

比如else不會(huì)換行。

比如，存在語(yǔ)法問(wèn)題，或者不能識(shí)別語(yǔ)法的時(shí)候，格式化會(huì)使用不了。這里我將最后一個(gè)端口加上","就不能格式化了。